If a vector PORT in the MHS is concatenated with either net_vcc or net_gnd and other single-bit or vector signals, or bit values, the port is incorrectly built. That is, VCC or GND is not concatenated together with the other signal(s) to create the correct size vector mapping.
For example, if you have a two-bit vector port concatenated with a single-bit signal and net_vcc in your "system.mhs" file, the bit mapped to net_vcc is not correctly generated:
PORT two_bit_vector = one_bit_signal & net_vcc
The resulting "system.vhd" will map only one_bit_signal to the first bit of two_bit_vector. The second bit will not be mapped to anything.
This occurs because PlatGen expands net_vcc and net_gnd to the appropriate vector size. Consequently, it is not legal to use net_vcc or net_gnd in a concatenation construct since the number of bits being consumed is not known.
Change the MHS to use constant drivers since this usage explicitly defines the bit-width contribution of the concatenation:
PORT two_bit_vector = one_bit_signal & 0b1