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AR# 20657

8.1i XST - "WARNING:Xst:2185 - "file.v" line xx: Possible simulation mismatch on property <property_name> of instance <inst> set by attribute"


Keywords: primitive, Verilog, meta, comment, pass, 7.1i

When I set an attribute on a primitive, XST issues a warning indicating a possible simulation mismatch:


//synthesis attribute INIT of U1 is "0"

FD u1 (.D(d), .C(c), .Q(q));

XST issues warning messages for meta-comments that have corresponding parameters on the primitives. The warning message is issued because meta-comments are not supported for simulation. When the meta-comment modifies the behavior of the primitive to which it is attached, a parameter must be added for proper simulation of the primitive.


XST supports modifying the properties of primitives through parameters. If the above warning message was generated as a result of Architecture Wizard or ECS, you can safely ignore the warning message. You can choose to filter out the warning messages through ISE. For more information, search for "filtering" in the ISE pull-down help menu. These issues are scheduled to be fixed in the next major release of the design tools.

XST supports modifying the properties of primitives through parameters as follows:


FD #(.INIT(1'b0) u1 (.D(d), .C(c), .Q(q));


FD u1 (.D(d), .C(c), .Q(q));
defparam u1.INIT = 1'b0;

Refer to the 8.1i Synthesis and Simulation Design Guide for Xilinx recommendations on how to pass the parameters. You can access this guide at:
AR# 20657
日期 01/07/2009
状态 Archive
Type 综合文章