There is a problem in the Embedded Tri-mode Ethernet MAC Wrapper v1.0 when EMAC is used in RGMII mode. Specifically, the top-level VHDL and Verilog wrappers (core_name_top.vhd and core_name_top.v) should have an IDELAY instantiated for the RGMII_RXC clock instead of the RGMII_RXD and RGMII_RX_CTL signals. The reason is that the RGMII specification requires a delay on the clock but not on the data or control signals.
A patch is available that correctly instantiates the IDELAY on the RGMII_RXC clock rather than the RGMII_RXD and RGMII_RX_CTL signals.
To obtain this fix, install the patch that is available in the Embedded Tri-mode Ethernet MAC Wrapper v1.0 Release Notes and Known Issues Answer Record (Xilinx Answer 20193).