When I perform back annotated timing simulation with the PCI Express Core, simulation does not work. Why?
During training, there are multiple millisecond time-outs in the LTSSM. For more information on this, please review section 4.2.6 of the PCI Base Specification v1.0a. For example, in some states polling takes up to 24 ms to complete. If the time-outs from each state are added, the training time becomes extremely long from a simulator's perspective. Once the design is placed on the board, training occurs as you would normally expect.
For information regarding functional simulation, see (Xilinx Answer 18530).