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AR# 20819

7.1i EDK SP2-opb_spi_v1_00_c - In Master-mode, there are glitches on the SPI clock when data and clock change simultaneously

描述

General Description:

In Master-mode, the SPI Core drives data changing on the clock edge. This causes data alignment problems on the downstream SPI device.

解决方案

This problem occurs if the local Slave Select on the Master (SPISEL) is left floating. To work around this, drive this line to a logic "1" in the MHS or top-level design by assigning the signal to "net_vcc."

AR# 20819
日期 12/15/2012
状态 Active
Type 综合文章
的页面