We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20919

8.2i CORE Generator - IP "readme.txt" file contains generic information for ".v" and ".vhd" files, which is not applicable for reference designs


Keywords: TEMAC, Tri-mode, Ethernet, MAC, readme, IP, Aurora, wrapper, HDL, simulation

At the end of an IP core generation, an "<IP-name>_README.txt" file is created for the new core. The README file lists the various files that were created for the core and gives the files' purpose. Does the information listed for ".v" and ".vhd" files apply to reference designs?

The README states, "Verilog (or VHDL) wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core."


No, the information does not apply to reference designs. The message is generically applied to every ".v" or ".vhd" file created by CORE Generator. However, for a reference design, such as Tri-Mode Ethernet MAC or Aurora, the complete design is provided including several VHDL and/or Verilog design files. For these reference designs, the ".v" or ".vhd" files are intended for synthesis and not just simulation.
AR# 20919
日期 04/08/2009
状态 Archive
Type 综合文章