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AR# 20995

7.1i ISE Simulator (ISIM) - Changing the generated HDL language from Verilog to VHDL or vice-versa does not work for schematic designs

描述

Keywords: ISE Simulator, ISIM, generated, VHDL, Verilog, schematic

Urgency: Standard

General Description:
When I use a schematic design, I cannot change the generated HDL language from Verilog to VHDL or vice-versa.

解决方案

This is a known issue for the ISE Simulator. To work around this problem, manually edit the .tbw file so that it points to the correct file name.

If changing from Verilog to VHDL:

1. Open the .tbw file in a text editor.
2. Go to the second line.
3. Look for the .vf file name : <filename>.vf
4. Change the extenstion on the file name : <filename>.vhf
5. Save the .tbw file.

If going from VHDL to Verilog:

1. Open the .tbw file in a text editor.
2. Go to the second line.
3. Look for the .vhf file name : <filename>.vhf
4. Change the extenstion on the file name : <filename>.vf
5. Save the .tbw file.

This issue will be fixed in the ISE 8.1i design tools.
AR# 20995
日期 10/16/2008
状态 Archive
Type 综合文章
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