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AR# 21003

7.1i CompXLib - SmartModels are not getting compiled for VHDL and Verilog

描述

Keywords: 6.3i, error, after, run, same, directory

Urgency: Standard

General Description:
When compiling VHDL and Verilog, both of the SmartModel wrappers are not getting compiled for the latter language. Why does this occur?

解决方案

This is an issue with CompXLib . When both of the languages are used, CompXLib will only compile for Verilog and not compile for VHDL.

Always compile using the "-w" switch. This will overwrite the libraries, allowing you to work around the problem.

This problem has been fixed in the latest 7.1i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 7.1i Service Pack 2.
AR# 21003
日期 11/18/2008
状态 Archive
Type 综合文章
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