AR# 21006

Virtex-II Pro RocketIO - Solutions List

描述

Keywords: resolutions, Answer Records, remedy, fix

Urgency: Standard

General Description:
This Answer Record contains a solutions list of all Xilinx Answer Records pertaining to Virtex-II Pro RocketIO.

解决方案

1

General

(Xilinx Answer 14366) - Virtex-II Pro RocketIO - What is the difference between SmartModel and HSPICE models?
(Xilinx Answer 15028) - Virtex-II Pro RocketIO - Does RocketIO support pre-emphasis (pre-conditioning)?
(Xilinx Answer 15034) - Virtex-II Pro RocketIO - Is internal AC coupling available?
(Xilinx Answer 15035) - Virtex-II Pro RocketIO - How many non-transitioning bits can the CDR unit's PLL withstand? In other words, what is the run-length limit?
(Xilinx Answer 15036) - Virtex-II Pro RocketIO - Is it possible to program the CDR unit's run-length limit?
(Xilinx Answer 15037) - Virtex-II Pro RocketIO - Does packaging (i.e., wire-bonded or Flip-Chip) introduce speed limitations?
(Xilinx Answer 15039) - Virtex-II Pro RocketIO - Is it possible to utilize a single CDR unit for multiple channels that are bonded together?
(Xilinx Answer 15047) - Virtex-II Pro RocketIO - Frequency offset (specified in ppm, or parts-per-million) and jitter (specified in seconds) seem very similar. What is the difference between these?
(Xilinx Answer 15049) - Virtex-II Pro RocketIO - If 8B/10B decoding is disabled, what encoding scheme is recommended?
(Xilinx Answer 15052) - Virtex-II Pro RocketIO - Does RocketIO support auto-negotiation?
(Xilinx Answer 15055) - Virtex-II Pro RocketIO - What are the Automatic lock-to-reference functions?
(Xilinx Answer 15064) - Virtex-II Pro RocketIO - Can each transceiver run independently in regards to clock rate?
(Xilinx Answer 16170) - Virtex-II Pro RocketIO - Is there a temperature derating factor for the RocketIO?
(Xilinx Answer 20732) - Virtex-II Pro RocketIO Transceiver User Guide v2.5 - Typographical errors in 8B/10B Valid Data Characters Table

2

Logic Design and Simulation

(Xilinx Answer 13926) - Virtex-II Pro RocketIO - What are the latencies from TXDATA to TXN/TXP and from RXN/RXP to RXDATA?
(Xilinx Answer 14669) - Virtex-II Pro RocketIO - Why are TX_BUFFER_USE and RX_BUFFER_USE always set to TRUE? Can I change them?
(Xilinx Answer 14888) - Virtex-II Pro RocketIO - What is the size of the receive (RX) elastic buffer?
(Xilinx Answer 14920) - Virtex-II Pro RocketIO - How do I ensure that my design will not overflow or underflow the RX (receiver) elastic buffer because of RX/TX clock differences (clock correction)?
(Xilinx Answer 14971) - Virtex-II Pro RocketIO - BREFCLK and RXRECCLK can drive FPGA internal logic?
(Xilinx Answer 14986) - Virtex-II Pro RocketIO - What is the minimum time the POWERDOWN signal should be asserted?
(Xilinx Answer 14994) - Virtex-II Pro RocketIO - For a 32-bit data path, is it possible to guarantee comma alignment in bits [31..24] if ALIGN_COMMA_MSB = TRUE?
(Xilinx Answer 15050) - Virtex-II Pro RocketIO - Does RocketIO support channel bonding?
(Xilinx Answer 15051) - Virtex-II Pro RocketIO - Can the Tx FIFO be bypassed?
(Xilinx Answer 15053) - Virtex-II Pro RocketIO - If an invalid K character is sent to the 8B/10B encoder (indicated by assertion of TXKERR), what is transmitted? Will the corresponding data word be transmitted instead?
(Xilinx Answer 15057) - Virtex-II Pro RocketIO - Is the REFCLK input required only for data transmission, or is it required for both transmission and reception?
(Xilinx Answer 15058) - Virtex-II Pro RocketIO - Should the REFCLK input be driven by a DCM?
(Xilinx Answer 15059) - Virtex-II Pro RocketIO - Should the REFCLK input be routed through a BUFG?
(Xilinx Answer 15061) - Virtex-II Pro RocketIO - Can the REFCLK input of any given transceiver be changed dynamically?
(Xilinx Answer 15062) - Virtex-II Pro RocketIO - When multiplexing two different REFCLKs, can I multiplex the two IBUFG outputs and use a single DCM for the USRCLKs?
(Xilinx Answer 15063) - Virtex-II Pro RocketIO - If I am using a 2-byte data path, can I forego a DCM and drive the USRCLK and USRCLK2 inputs with a REFCLK input?
(Xilinx Answer 15066) - Virtex-II Pro RocketIO - If a data width is specified for the GT_CUSTOM primitive, must I still zero-pad data and byte-map control signals when using 1-byte and 2-byte paths?
(Xilinx Answer 15067) - Virtex-II Pro RocketIO - Is clock correction an independent operation for each transceiver?
(Xilinx Answer 15670) - Virtex-II Pro RocketIO - The RXCOMMADET output stays High for multiple cycles
(Xilinx Answer 16318) - Virtex-II Pro RocketIO - Guidelines for Channel-Bonding Attributes (CHAN_BOND_WAIT, CHAN_BOND_OFFSET, CHAN_BOND_LIMIT) and Operation
(Xilinx Answer 16752) - Virtex-II Pro RocketIO - ALIGN_COMMA_MSB can never be set to TRUE to override the default FALSE. When can I use ALIGN_COMMA_MSB?
(Xilinx Answer 17103) - Virtex-II Pro RocketIO - What is a reliable way to determine that a transceiver is ready for operation after it is powered down?
(Xilinx Answer 19749) - Virtex-II Pro RocketIO - Channel Bonding and Clock Correction Sequence Intervals
(Xilinx Answer 20009) - Virtex-II Pro RocketIO - What is the latency for the current running disparity to be reflected on TXRUNDISP and/or RXRUNDISP?
(Xilinx Answer 20719) - Virtex-II Pro RocketIO - When is RXCHECKINGCRC asserted after receiving the EOF?
(Xilinx Answer 21147) - Virtex-II Pro RocketIO - After deasserting RXRESET why are RXDATA, RXCOMMADET and other RX signals 'X' for a time?
(Xilinx Answer 21304) - Virtex-II Pro, Virtex-II Pro X, Virtex-4 FX RocketIO- Is there any difference in the way the TXINHIBIT signal works in the Virtex-II Pro vs Virtex-II Pro X vs. Virtex-4 MGTs?
(Xilinx Answer 21305) - Virtex-II Pro, Virtex-II Pro X, Virtex-4 FX RocketIO - Is there any difference in the way the TXRESET signal works in the Virtex-II Pro vs. Virtex-II Pro X vs. Virtex-4 MGTs?
(Xilinx Answer 21331) - Virtex-II Pro, Virtex-II Pro X, Virtex-4 RocketIO - # Attribute Syntax Error : The Attribute ALIGN_COMMA_MSB on GT* instance *.gt*_1 is set to 0 0. Legal values for this attribute are TRUE or FALSE.
(Xilinx Answer 21541) - Virtex-II Pro, Virtex-II Pro-X, Virtex-4 RocketIO - Synplify 8.0 - ERROR:LIT:241 - Attribute MCOMMA_32B_VALUE on GT instance

3

Board

(Xilinx Answer 14136) - Virtex-II Pro RocketIO - What oscillators should be used for the reference clock (REFCLK) input?
(Xilinx Answer 14606) - Virtex-II Pro RocketIO - How do I perform clock correction on a multiple comma sequence (rather than a single comma)?
(Xilinx Answer 14747) - Virtex-II Pro RocketIO - Do I need to power the transceivers if they are not used? How should I handle the unused pins?
(Xilinx Answer 14748) - Virtex-II Pro RocketIO - How should unused RocketIO transceiver pins be handled?
(Xilinx Answer 14863) - Virtex-II Pro RocketIO - Should the GNDA (analog Ground) of a RocketIO transceiver be connected to the PCB Ground?
(Xilinx Answer 14892) - Virtex-II Pro RocketIO - How do I set up the power-filtering network for multiple RocketIO transceivers on a PCB?
(Xilinx Answer 14953) - Virtex-II Pro RocketIO - Is it possible for channel bonding to be performed across multiple Virtex-II Pro chips?
(Xilinx Answer 14978) - Virtex-II Pro RocketIO - What connectors can be used with RocketIO transceivers?
(Xilinx Answer 15054) - Virtex-II Pro RocketIO - Behavior of AVCCAUX (RX/TX) supply currents at device power up before VCCINT and VCCAUX supplies are powered up
(Xilinx Answer 15056) - Virtex-II Pro RocketIO - Is there a recommended signaling standard that should be used for the REFCLK input?
(Xilinx Answer 15060) - Virtex-II Pro RocketIO - What if I have a single REFCLK driving two or more MGTs on opposite sides of the chip? In this case, should REFCLK be routed through a BUFG to minimize skew?
(Xilinx Answer 15065) - Virtex-II Pro RocketIO - Is it possible to put the Tx pins into a 3-state condition?
(Xilinx Answer 15228) - Virtex-II Pro RocketIO - Why are all GNDA pins in the Virtex-II Pro pin-outs repeated?
(Xilinx Answer 16629) - Virtex-II Pro RocketIO - RXRECCLK is not generated if TXUSRCLK and TXUSRCLK2 are not driven
(Xilinx Answer 16656) - Virtex-II Pro RocketIO - MGT Characterization Summary
(Xilinx Answer 16692) - Virtex-II Pro RocketIO - Common-mode noise on RocketIO outputs
(Xilinx Answer 16700) - Virtex-II Pro RocketIO - Can the MGT interoperate with an LVDS when they are DC-coupled?
(Xilinx Answer 16748) - Virtex-II Pro RocketIO - How do I use only one oscillator for both the top and bottom BREFCLK inputs?
(Xilinx Answer 16812) - Virtex-II Pro RocketIO - What is the maximum allowable skew between RXN and RXP?
(Xilinx Answer 17089) - Virtex-II Pro RocketIO - How can I derive 1.6-1.8 volts necessary for the VTRX supply in an AC coupled link without a separate regulator?
(Xilinx Answer 17711) - Virtex-II Pro RocketIO - What is the tolerance of the internal 50- and 75-ohm termination resistors?
(Xilinx Answer 17889) - Virtex-II Pro RocketIO - Is the reference clock used in the receiver logic after the PLL has locked?
(Xilinx Answer 18017) - Virtex-II Pro RocketIO - Why is the power consumption for VTRX pins zero?
(Xilinx Answer 18192) - Virtex-II Pro RocketIO - Does RocketIO have specific power sequencing (VCCO / VCCAUX)?
(Xilinx Answer 18590) - Virtex-II Pro RocketIO - Are there other recommended regulators besides the LT1963?
(Xilinx Answer 18681) - Virtex-II Pro RocketIO - The recommended reference clock oscillators cover only the commercial temperature range. What oscillators should I use for the industrial range?
(Xilinx Answer 18768) - Virtex-II Pro RocketIO - What is the maximum cycle-cycle change in RXRECCLK during phase capture?
(Xilinx Answer 18849) - Virtex-II Pro RocketIO - CDR circuit does not work, invalid data is received, RXRECCLK is stuck at 1 or 0. Failure is corrected after POWERDOWN or reconfiguration
(Xilinx Answer 18872) - Virtex-II Pro RocketIO - Which Virtex-II Pro device/package combination has bypass capacitors on RocketIO power supply pins?
(Xilinx Answer 18999) - Virtex-II Pro RocketIO - How can I increase the eye height at the receiver if the channel is too lossy?
(Xilinx Answer 19150) - Virtex-II Pro RocketIO - What is the termination set to before power is applied, after power is applied (before configuration), and after configuration?
(Xilinx Answer 19270) - Virtex-II Pro RocketIO - How do I choose the AC coupling capacitors for speeds other than 3.125 Gb/s?
(Xilinx Answer 19699) - Virtex-II Pro, Virtex-II Pro X, Virtex-4 FX RocketIO - Board Debug Steps
(Xilinx Answer 19895) - Virtex-II Pro RocketIO - Can AVCCAUXTX/AVCCAUXRX and VTTX/VTRX power filtering networks be shared if the MGT is used as a Transmitter (TX) only or Receiver (RX) only?
(Xilinx Answer 21258) - Virtex-II Pro RocketIO - When AC-coupled how much current flows through VTRX?

4

Standards

(Xilinx Answer 13928) - Virtex-II Pro RocketIO - Gigabit Ethernet compliance
(Xilinx Answer 13929) - Virtex-II Pro RocketIO - XAUI compliance
(Xilinx Answer 13931) - Virtex-II Pro RocketIO - PCI Express compliance
(Xilinx Answer 13932) - Virtex-II Pro RocketIO - Rapid I/O compliance
(Xilinx Answer 13934) - Virtex-II Pro RocketIO - InfiniBand compliance
(Xilinx Answer 13935) - Virtex-II Pro RocketIO - Serial ATA (SATA) compliance
(Xilinx Answer 13936) - Virtex-II Pro RocketIO - Fibre Channel Compliance
(Xilinx Answer 14607) - Virtex-II Pro RocketIO - CRC details for Gigabit Ethernet and Fibre Channel
(Xilinx Answer 14608) - Virtex-II Pro RocketIO - Gigabit Ethernet interoperability has been verified
(Xilinx Answer 18371) - Virtex-II Pro RocketIO, Ethernet - Is there a maximum Ethernet preamble when using CRC?
(Xilinx Answer 18525) - Virtex-II Pro RocketIO - In the RocketIO Characterization Report, what does the XAUI jitter tolerance plot mean?
(Xilinx Answer 19312) - SMA to SATA module - Module Usage
(Xilinx Answer 19568) - Virtex-II Pro RocketIO - Fibre Channel Arbitrated Loop (FC_AL) compliance
(Xilinx Answer 19750) - Virtex-II Pro RocketIO - Usage of CRC in Fibre Channel Mode
(Xilinx Answer 19928) - Virtex-II Pro RocketIO - Fibre Channel 2Gbps jitter compliance
(Xilinx Answer 20293) - Virtex-II Pro, RocketIO - How do I pre-determine the disparity for TX as in the case of Fibre Channel?

AR# 21006
日期 07/25/2005
状态 Active
Type 综合文章