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AR# 21008

7.1i Service Pack 1 NetGen, Timing Simulation Virtex-4 - The S and R value is left unconnected on the ODDR, which causes timing simulations to fail

描述

Keywords: SimPrim, ERROR, ModelSim, NC-VHDL, NC-Verilog, VCS

Urgency: Standard

General Description:
When performing a timing simulation in ISE 7.1i Service Pack 1, the ODDR does not function correctly and there are only Xs at the output.

解决方案

This problem has been fixed in the latest 7.1i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 7.1i Service Pack 2.
AR# 21008
日期 11/16/2008
状态 Archive
Type 综合文章
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