AR# 2104

SYNPLIFY - How do I instantiate RAM or ROM in HDL (Verilog/VHDL)?

描述

General Description:

How do I instantiate RAM or ROM in HDL (Verilog/VHDL) using Synplify?

解决方案

You can instantiate RAM/ROM cells by using the Xilinx family library supplied with Synplify. Please see (Xilinx Answer 244) for details of instantiating Xilinx-specific cells.

The following example illustrates the creation of a 16x8 ROM using the Xilinx ROM16x1 component:

`include "<install_path>/lib/xilinx/xc4000.v"

module rom_16x8 (o, a);

input [3:0] a;

output [7:0] o;

ROM16X1 u0 (.O (o[0]), .A0 (a[0]), .A1 (a[1]), .A2 (a[2]), .A3 (a[3]))

/* synthesis xc_props="INIT=FFFF" */;

ROM16X1 u1 (.O (o[1]), .A0 (a[0]), .A1 (a[1]), .A2 (a[2]), .A3 (a[3]))

/* synthesis xc_props="INIT=ABCD" */;

ROM16X1 u2 (.O (o[2]), .A0 (a[0]), .A1 (a[1]), .A2 (a[2]), .A3 (a[3]))

/* synthesis xc_props="INIT=BCDE" */;

ROM16X1 u3 (.O (o[3]), .A0 (a[0]), .A1 (a[1]), .A2 (a[2]), .A3 (a[3]))

/* synthesis xc_props="INIT=CDEF" */;

ROM16X1 u4 (.O (o[4]), .A0 (a[0]), .A1 (a[1]), .A2 (a[2]), .A3 (a[3]))

/* synthesis xc_props="INIT=CCDD" */;

ROM16X1 u5 (.O (o[5]), .A0 (a[0]), .A1 (a[1]), .A2 (a[2]), .A3 (a[3]))

/* synthesis xc_props="INIT=0000" */;

ROM16X1 u6 (.O (o[6]), .A0 (a[0]), .A1 (a[1]), .A2 (a[2]), .A3 (a[3]))

/* synthesis xc_props="INIT=0010" */;

ROM16X1 u7 (.O (o[7]), .A0 (a[0]), .A1 (a[1]), .A2 (a[2]), .A3 (a[3]))

/* synthesis xc_props="INIT=1100" */;

endmodule

The following example illustrates the creation of a 16x8 ROM using the Xilinx ROM16x1 component:

library IEEE;

use IEEE.std_logic_1164.all;

library xc4000;

use xc4000.components.all;

library synplify;

use synplify.attributes.all;

entity rom_16x1 is

generic (init_val : string := "0000" );

port (O : out std_logic;

A3, A2, A1, A0: in std_logic);

end rom_16x1;

architecture xilinx of rom_16x1 is

attribute xc_props: string;

attribute xc_props of u1 : label is "INIT=" & init_val;

begin

U1 : ROM16X1 port map (O => O, A0 => A0, A1 => A1, A2 => A2, A3 => A3);

end xilinx;

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity rom_16x8 is

port (o: out std_logic_vector(7 downto 0);

a: in std_logic_vector(3 downto 0));

end rom_16x8;

architecture xilinx of rom_16x8 is

component rom_16x1

generic (init_val: string := "0000");

port (O : out std_logic;

A3, A2, A1, A0 : in std_logic);

end component;

begin

U0 : rom_16x1 generic map ("FFFF")

port map (O => o(0), A0 => a(0), A1 => a(1), A2 => a(2), A3 => a(3));

U1 : rom_16x1 generic map ("ABCD")

port map (O => o(1), A0 => a(0), A1 => a(1), A2 => a(2), A3 => a(3));

U2 : rom_16x1 generic map ("BCDE")

port map (O => o(2), A0 => a(0), A1 => a(1), A2 => a(2), A3 => a(3));

U3 : rom_16x1 generic map ("CDEF")

port map (O => o(3), A0 => a(0), A1 => a(1), A2 => a(2), A3 => a(3));

U4 : rom_16x1 generic map ("CCDD")

port map (O => o(4), A0 => a(0), A1 => a(1), A2 => a(2), A3 => a(3));

U5 : rom_16x1 generic map ("0000")

port map (O => o(5), A0 => a(0), A1 => a(1), A2 => a(2), A3 => a(3));

U6 : rom_16x1 generic map ("0010")

port map (O => o(6), A0 => a(0), A1 => a(1), A2 => a(2), A3 => a(3));

U7 : rom_16x1 generic map ("1100")

port map (O => o(7), A0 => a(0), A1 => a(1), A2 => a(2), A3 => a(3));

end xilinx;

The following example illustrates the creation of a 16x4 RAM using the Xilinx RAM16X1S component:

`include "/products/synplify/lib/xilinx/xc4000.v"

module RAM_INIT_EX1 (DATA_BUS, ADDR, WE, CLK);

input [3:0] ADDR;

inout [3:0] DATA_BUS;

input WE, CLK;

wire [3:0] DATA_OUT;

// Only for Simulation -- the defparam will not synthesize

// Use the defparam for RTL simulation.

// There is no defparam needed for Post-PAR simulation.

// synthesis translate_off

defparam RAM0.INIT="0101", RAM1.INIT="AAAA",

RAM2.INIT="FFFF", RAM3.INIT="5555";

// synthesis translate_on

assign DATA_BUS = !WE ? DATA_OUT : 4'hz;

// Instantaition of 4 16X1 Synchronous RAMs

// Use the xc_props attribute to pass the INIT property

RAM16X1S RAM3 (.O (DATA_OUT[3]), .D (DATA_BUS[3]),

.A3 (ADDR[3]), .A2 (ADDR[2]), .A1 (ADDR[1]),

.A0 (ADDR[0]), .WE (WE), .WCLK (CLK))

/* synthesis xc_props="INIT=5555" */;

RAM16X1S RAM2 (.O (DATA_OUT[2]), .D (DATA_BUS[2]),

.A3 (ADDR[3]), .A2 (ADDR[2]), .A1 (ADDR[1]),

.A0 (ADDR[0]), .WE (WE), .WCLK (CLK))

/* synthesis xc_props="INIT=FFFF" */;

RAM16X1S RAM1 (.O (DATA_OUT[1]), .D (DATA_BUS[1]),

.A3 (ADDR[3]), .A2 (ADDR[2]), .A1 (ADDR[1]),

.A0 (ADDR[0]), .WE (WE), .WCLK (CLK))

/* synthesis xc_props="INIT=AAAA" */;

RAM16X1S RAM0 (.O (DATA_OUT[0]), .D (DATA_BUS[0]),

.A3 (ADDR[3]), .A2 (ADDR[2]), .A1 (ADDR[1]),

.A0 (ADDR[0]), .WE (WE), .WCLK (CLK))

/* synthesis xc_props="INIT=0101" */;

endmodule

The following example illustrates the creation of a 16x4s RAM using the Xilinx RAM16x1S component:

library IEEE;

use IEEE.std_logic_1164.all;

library xc4000;

use xc4000.components.all;

library synplify;

use synplify.attributes.all;

entity ram_16x1s is

generic (init_val : string := "0000" );

port (O : out std_logic;

D : in std_logic;

A3, A2, A1, A0: in std_logic;

WE, CLK : in std_logic);

end ram_16x1s;

architecture xilinx of ram_16x1s is

attribute xc_props: string;

attribute xc_props of u1 : label is "INIT=" & init_val;

begin

U1 : RAM16X1S port map (O => O, WE => WE, WCLK => CLK, D => D, A0 => A0, A1 => A1, A2 => A2, A3 => A3);

end xilinx;

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity ram_16x4s is

port (o: out std_logic_vector(3 downto 0);

we : in std_logic;

clk : in std_logic;

d: in std_logic_vector(3 downto 0);

a: in std_logic_vector(3 downto 0));

end ram_16x4s;

architecture xilinx of ram_16x4s is

component ram_16x1s

generic (init_val: string := "0000");

port (O : out std_logic;

D : in std_logic;

A3, A2, A1, A0 : in std_logic;

WE, CLK : in std_logic);

end component;

begin

U0 : ram_16x1s generic map ("FFFF")

port map (O => o(0), WE => we, CLK => clk, D => d(0), A0 => a(0), A1 => a(1), A2 => a(2), A3 => a(3));

U1 : ram_16x1s generic map ("ABCD")

port map (O => o(1), WE => we, CLK => clk, D => d(1), A0 => a(0), A1 => a(1), A2 => a(2), A3 => a(3));

U2 : ram_16x1s generic map ("BCDE")

port map (O => o(2), WE => we, CLK => clk, D => d(2), A0 => a(0), A1 => a(1), A2 => a(2), A3 => a(3));

U3 : ram_16x1s generic map ("CDEF")

port map (O => o(3), WE => we, CLK => clk, D => d(3), A0 => a(0), A1 => a(1), A2 => a(2), A3 => a(3));

end xilinx;

AR# 2104
日期 12/15/2012
状态 Active
Type 综合文章