This Answer Record contains the Release Notes for the LogiCORE Gigabit Ethernet MAC v6.0 Core, released in 7.1i IP Update #1 and included in 7.1i IP Update #2 and 7.1i IP Update #3, which includes the following:
- New Features in v6.0
- Bug Fixes in v6.0
- Known Issues in v6.0
NOTE: No updates or modifications were made to the Gigabit Ethernet MAC v6.0 Core as a result of 7.1i IP Update #2 or IP Update #3; thus, the information included below still applies to 7.1i IP Update #1, IP Update #2, and IP Update #3.
For installation instructions and design tools requirements, see (Xilinx Answer 21019).
New Features in v6.0
- Added support for Spartan-3E
- Added support for ISE 7.1i
- New UniSim-based functional models (VHDL or Verilog) for faster simulations
- Directory structure updated to support CORE Generator 7.1i
- New FIFO added to Example Design, replacing the previously supplied loopback-only FIFO
Bug Fixes in v6.0
- CR 203037: Issues when transmitting jumbo frames when the jumbo frame option is disabled
Known Issues in v6.0
1. Spartan-3E support has been reinstated for all speed grade devices. Originally, all Spartan-3E support was withdrawn because it was not possible to meet the 2 ns setup and 0 ns hold I/O timing as defined in the IEEE 802.3-2002 specification using the latest Spartan-3E speed files at the time. The Spartan-3E -4 and -5 speed grade files have improved enough to where the I/O timing can now be met.
2. The IOSTANDARD constraints for the RGMII interface are incorrect. For more information on this issue and details on how to work around it, refer to (Xilinx Answer 21324).
3. The implementation script does not generate bitstreams for the Example Design if the target device is Spartan-3E. For more information, refer to (Xilinx Answer 21056).
4. When targeting the core with configurations that use DCMs to Virtex-4 devices, new DCM timing parameters need to be considered that might require the use of the DCM_STANDBY macro. For more information, refer to (Xilinx Answer 21735).