This Answer Record contains the Release Notes for the LogiCORE Tri-mode Ethernet MAC v2.1 Core, released in 7.1i IP Update #1 and included in 7.1i IP Update #2 and 7.1i IP Update #3, which includes the following:
- New Features in v2.1
- Bug Fixes in v2.1
- Known Issues in v2.1
NOTE: No updates or modifications were made to the Tri-mode Ethernet MAC v2.1 Core as a result of 7.1i IP Update #2 or IP Update #3; thus, the information included below still applies to 7.1i IP Update #1, IP Update #2, and IP Update #3.
For installation instructions and design tools requirements, see (Xilinx Answer 21019).
New Features in v2.1
- Added support for Spartan-3E
- Added support for ISE 7.1i
- New UniSim-based functional models (VHDL or Verilog) for faster simulations
- Added optional clock enable inputs on the transmit and receive client side to reduce the number of BUFGs needed
- Added option to vary the number of address table entries
- Directory structure updated to support CORE Generator 7.1i
Bug Fixes in v2.1
- CR196253: Incorrect error checking on first Half Duplex frame received after a switch from Full to Half Duplex
- CR198744: 1Gb/s Half Duplex behavior improved
Known Issues in v2.1
1. Spartan-3E support has been reinstated for all speed grade devices. Originally, all Spartan-3E support was withdrawn because it was not possible to meet the 2 ns setup and 0 ns hold I/O timing as defined in the IEEE 802.3-2002 specification using the latest Spartan-3E speed files at the time. The Spartan-3E -4 and -5 speed grade files have improved enough that the I/O timing can now be met.
2. The IOSTANDARD constraints for the RGMII interface are incorrect. For more information on this issue and details on how to work around it, refer to (Xilinx Answer 21325).
3. When targeting the core with configurations that use DCMs to Virtex-4 devices, new DCM timing parameters need to be considered that might require the use of the DCM_STANDBY macro. For more information, refer to (Xilinx Answer 21888).
4. The implementation script does not generate bitstreams for the Example Design if the target device is Spartan-3E. For more information, refer to (Xilinx Answer 21056).
5. Problem with the ".ucf" constraint file for Spartan-3E that causes setup/hold errors in simulation. For more information on this issue, see (Xilinx Answer 21664). To resolve this issue, install the patch below and regenerate the core.
6. When generating with the address filter, the users guide documents that, by default, the Address Filter Mode will be set to promiscuous. In the v2.1 core, the default is actually that the Address Filter is enabled when the core has been generated with the optional address filter. This is no longer the case and in the latest version of the core the default mode matches the documentation and is promiscuous.
To resolve issue #5 from above, apply the following patch to the Xilinx ISE installation with 7.1i Service Pack 3 and IP Update #1 or later:
NOTE: If 7.1i IP Update #1 was installed followed by this patch and then 7.1i IP Update #2 or IP Update #3 was installed, the patch must be reinstalled because IP Update #2 and IP Update #3 will overwrite the existing patched files with the original incorrect ones.
Install the patch as follows:
1. Extract the contents of the ".zip", ".gtar,gz", or "tar.gz" archive to the root directory of the Xilinx installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure pre-defined in the archive.
Determine the Xilinx installation directory by entering the following at the command prompt:
UNIX or Linux
Determine the Xilinx installation directory by typing the following:
NOTE: You might need to have system administrator privileges to install the patch.
2. After installing the patch, regenerate the LogiCORE Tri-mode Ethernet MAC v2.1 Core from CORE Generator. The core and supporting files produced will contain the fixes mentioned above.