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AR# 21048

LogiCORE Fibre Channel v2.0 Core - Release Notes and Known Issues for the Fibre Channel Core


General Description: 

This Answer Record contains the Release Notes for the LogiCORE Fibre Channel v2.0 Core, released in 7.1i IP Update #1 and included in 7.1i IP Update #2 and IP Update #3, which includes the following: 


- New Features in v2.0 

- Bug Fixes in v2.0 

- Known Issues in v2.0 


NOTE: No updates or modifications were made to the Fibre Channel v2.0 Core as a result of 7.1i IP Update #2 or IP Update #3; thus, the information included below still applies to 7.1i IP Update #1, IP Update #2, and IP Update #3. 


For installation instructions and design tools requirements, see (Xilinx Answer 21019).


New Features in v2.0 


- Added support for Virtex-4 

- Added support for ISE 7.1i 

- 4 Gb/s and 2 Gb/s / 4Gb/s multi-speed support added to Virtex-4 configuration 

- Added option to remove credit management block 

- Added optional hardware speed negotiation block 

- Added user-programmable inter-frame gap 

- New UniSim-based functional models (VHDL or Verilog) for faster simulations 

- Directory structure updated to support CORE Generator 7.1i 


Bug Fixes in v2.0 


- CR 193149: Statistics block slice-count reduction 

- CR 195350: 2 Gb/s IFG sometimes too short 

- CR 195566: Example design FIFO write pointer error 

- CR 199472: Receive statistics occasional miscounts on Rx10bErrCnt and RxOsdErrCnt 


Known Issues in v2.0 


1. During timing simulation of Multi-speed configurations there might be timing errors generated as the core changes speed. These can be safely ignored.  


2. The "mod_def_0_p" symbol pin is incorrectly labeled as "moddef_0_p" in the ASY symbol file. For more information on this issue and details on how to work around it, refer to (Xilinx Answer 21323)


3. Simulation fails in 7.1i Service Pack 3 because RX_LOS_INVALID_INCR and RX_LOS_THRESHOLD signals are missing from SmartModel. For more information on this issue, see (Xilinx Answer 21665). To resolve this issue, install the patch below and regenerate the core. 


4. When targeting the core with configurations that use DCMs to Virtex-4 devices, new DCM timing parameters need to be considered that may require the use of the DCM_STANDBY macro. For more information, refer to (Xilinx Answer 21885)


5. A Calibration Block for the Virtex-4 RocketIO must be used with ES devices. Please refer to UG090: Calibration Block User Guide, or contact your FAE for more details and instructions on how to connect the module to the MGTs DRP and other ports. The MGTs in the XAUI core are instantiated in the "FCMGT.v/.vhd" file. This file can be modified to instantiate GT11 Calibration Block. 




To resolve issue #3 from above, apply the following patch to the Xilinx ISE installation with 7.1i Service Pack 3 and IP Update #1 or later: 



NOTE: If 7.1i IP Update #1 was installed followed by this patch and then 7.1i IP Update #2 or IP Update #3 was installed, the patch will need to be reinstalled because IP Update #2 and IP Update #3 will overwrite the existing patched files with the original incorrect ones. 


Install the patch as follows: 

1. Extract the contents of the ".zip", ".gtar,gz", or "tar.gz" archive to the root directory of the Xilinx installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure pre-defined in the archive.  



Determine the Xilinx installation directory by entering the following at the command prompt: 

"echo %XILINX%" 


UNIX or Linux 

Determine the Xilinx installation directory by typing the following: 

"echo $XILINX" 


NOTE: You might need to have system administrator privileges to install the patch.  


2. After installing the patch, regenerate the LogiCORE Fibre Channel v2.0 Core from CORE Generator. The core and supporting files produced will contain the fixes mentioned above.

AR# 21048
日期 05/19/2014
状态 Archive
Type 综合文章