Three DCM timing parameters must be met to ensure that the DCMs meet their maximum frequency specifications across all conditions:
- TCONFIG: Maximum time to configure devices after VCCINT is applied (10 min). - DCM_INPUT_CLOCK_STOP: Maximum duration that CLKIN and CLKFB can be stopped (100 ms). - DCM_RESET: Maximum duration that RST can be held asserted (10 sec).
TCONFIG: Maximum time to configure devices after VCCINT is applied (10 min)
The TCONFIG specification is safely repeatable for any normal usage. Specifically, it can be repeated indefinitely if the time spent configured is at least twice as long as the time spent powered and unconfigured (on average). For example, if it takes three minutes to configure the FPGA after power up, it should remain in the configured state for at least six minutes (on average) to guarantee DCM maximum frequency operation.
If the FPGA cannot be configured within ten minutes after VCCINT has been applied, or if the amount of time spent for configuring is not at least twice the amount of time spent powered and unconfigured, use the Null Bitstream Solution described below.
Note the following: - This TCONFIG requirement applies only to VCCINT; VCCAUX and VCCO can potentially be applied long before configuration. - These TCONFIG statements assume that the DCM operates normally (i.e., toggles) after the device is configured. If the DCM input clocks stop or if the DCM is held in reset, an additional workaround is required. See the DCM_INPUT_CLOCK_STOP and DCM_RESET sections below.
Null Bitstream Solution
On board power up, Virtex-4 devices should be configured with the appropriate null bitstream provided by Xilinx. The null bitstream activates only the DCMs in the device and keeps the DCMs in continuous calibration mode (provide a slow clock to the DCMs, while setting all DCM outputs to High). When the system is ready, the devices can be reconfigured with the user bitstream.
These bitstreams have been fully verified and characterized by Xilinx.
To implement this solution, the board must have one of the following: - A permanent (nonremovable) reconfiguration pathway. - An additional small PROM on the board that is programmed using a qualified null bitstream provided by Xilinx.
For new designs, Xilinx recommends using a PROM and ensuring JTAG connectivity for both the PROM and FPGAs.
DCM_INPUT_CLOCK_STOP: Maximum duration that CLKIN and CLKFB can be stopped (100 ms)
DCM_RESET: Maximum duration that RST can be held asserted (10 sec)
Use the new DCM macro in designs stopping the DCM CLKIN or CLKFB for more than 100 ms or asserting DCM RST for more than ten seconds.
DCM_STANDBY Macro Solution
The DCM_STANDBY macro monitors the input clock, the feedback clock, and the reset to the DCM. If the input clock or the feedback clock is not toggling for more than 100 ms, or if the reset is asserted, the macro keeps the DCM in continuous calibration mode (provide a slow clock to the DCM, while setting all DCM outputs to High). When the input clock resumes or reset is deasserted, the macro resets the DCM and continues monitoring.
NOTE: For important details about the DCM_STANDBY macro, review the "readme.doc" file included in the download.
Using the Macro
- v2.20 of the Verilog DCM macro is now available.
- All customers starting new designs should use this version of the macro. - For customers with existing designs, upgrade to the 2.20 version of the macro if possible. This is not a requirement, since the older versions (0.8, 0.9, 1.0, 2.00, and 2.10 ) are functionally correct. Xilinx is currently updating the link for these files; you can contact Technical support for access to these files.
Improvements in v2.20
- v2.20s has been created for Synplify synthesis tool support. - A TIG constraint has been added to eliminate timing errors in cross-clock domain timing analysis.
Improvements in v2.10
- Smaller design uses fewer resources (~50 slices). - Simulation no longer shows glitching on LOCKED during DCM reset. NOTE: This was a simulation issue only in v0.8, v0.9, and v1.0. - Internal clocks are constrained. - DO outputs reflect DCM status when the macro is inactive.
3. Replace existing DCM instantiations in your design with the new DCM_STANDBY macro. Either insert the code in your existing design, or keep the macro in your design directories. If you have multiple Virtex-4 FPGA designs, you can place the DCM_STANDBY code in your library directory instead of keeping a copy in every design directory. If you have multiple DCM instantiations a the DCM_STANDBY macro a unique component name is required for each: VHDL = generic "COMPNAME", verilog = parameter "COMPNAME." 4. Make sure all DCM attributes and constraints are applied to the new DCM macro instances. 5. If you are using ISE 8.1i Service Pack 1 and Service Pack 2 running Verilog simulation, see (Xilinx Answer 22820).
This version of the macro is not recommended for new designs. Please use v2.00 or greater for new designs.
Contact Xilinx Technical Support for information regarding previous versions of the DCM NBTI macro.
Virtex-4 LX/SX Production Step 2 and higher, Virtex-4 FX ES4 and Production devices do not require the DCM_STANDBY macro. Instead, ISE design tools automatically insert a small macro for designs with DCMs targeting these devices. For more information on the automatically inserted design tools macro for Virtex-4 LX/SX Production Step 2 and higher, Virtex-4 FX ES4 and Production devices only, see (Xilinx Answer 21435).