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AR# 21188

Virtex-4 RocketIO - Why is CLK_COR_SEQ_1_x not working correctly in simulation?

描述

Clock Correction on the CLK_COR_SEQ_1_x does not seem to be working correctly in simulation. Why is that?

解决方案

This problem has been fixed in the latest 7.1i Service Pack available at: 

http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 7.1i Service Pack 2. 

 

In the meantime, you can work around this problem by switching to CLK_COR_SEQ_2_x. This affects only simulation.

AR# 21188
日期 05/19/2014
状态 Archive
Type 综合文章
的页面