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AR# 21196

7.1i NetGen, Timing Simulation Virtex-4 - The IDELAY component does show any delays at the output during a timing simulation

描述

Keywords: simulate, SimPrim, idelay, x_idelay, delay, output, timing

Urgency: Standard

General Description:
During a timing simulation, the back-annotated netlist does not contain the following two generics/parameters:

IOBDELAY_TYPE
IOBDELAY_VALUE

This causes the IDELAY not to show any delays from Input to Output.

解决方案

This problem has been fixed in the latest 7.1i Service Pack, available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 7.1i Service Pack 2.
AR# 21196
日期 11/16/2008
状态 Archive
Type 综合文章
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