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AR# 21222

Virtex-II Pro X RocketIO - What is the lane-to-lane skew between the RocketIO, and how do I control/reduce it?

描述

What is the lane-to-lane skew between the RocketIO, and how do I control/reduce it?

解决方案

What is the lane-to-laneTX skew?

There are three components to the TX skew, as follows:

USRCLK Phase

USRCLK phase results in a one-word skew.

For an internal data path of 32 bits, it is 32 UI (Unit Interval).

For an internal data path of 40 bits, it is 40 UI (Unit Interval).

PISO Alignment

PISO clock alignment can also have as much as a one-word skew, depending on the PLL alignment on power up.

For an internal data path of 32 bits, it is 32 UI (Unit Interval).

For an internal data path of 40 bits, it is 40 UI (Unit Interval).

BREFCLK Routing Skew

BREFCLK routing skew should generally be 2 UI at 2.5Gbps, and a maximum of 4 UI.

Consequently, the absolute worst case number for an internal data path width of 32 bits is 68 UI and for 40 bits it is 84 UI. 

In practice it is always less because the PISO and USRCLK skews tend to cancel each other out; this is pending characterization.

Is this skew guaranteed and stable?

These skews are deterministic after power-up; this has been tested and does not vary once the device is stable.

Are there ways to control or mitigate the skew?

To mitigate skew, you can eliminate the one-word skew due to the clock phase by using a closed loop approach that allows for encoded data.

This method includes sending a training pattern and observing each lane at the receiver to determine the skew, or reporting back when each lane is aligned.

The transmit side can adjust the fabric interface delay until the lanes are aligned. This solution can be a simple state machine that tries the various combinations of delay until each lane is aligned. 

The delay can be a simple two-stage pipeline delay on the fabric user interface with optional bypassing on each stage to adjust the delay.

AR# 21222
日期 06/21/2017
状态 Active
Type 综合文章
器件
  • Virtex-II Pro X
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