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AR# 21280

7.1i ISE - Project Navigator source selection automatically goes to the "top" level when a lower-level module is opened


Keywords: Highlight, Verilog, VHDL, selected, hierarchy, selection

Urgency: Standard

General Description:
I can single-click to select any source in the hierarchy of a design. Project Navigator highlights and selects that module as the active source. Now if I double-click that lower-level to open it, it opens, but the highlighting and selection returns to the top module of the design. It should remain on the lower at this point.


This problem has been fixed in the latest 7.1i Service Pack available at:
The first service pack containing the fix is 7.1i Service Pack 2.
AR# 21280
日期 12/13/2006
状态 Archive
Type 综合文章