We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21284

v2.3 CORE Generator Aurora - Release Notes and Known Issues


General Description:

This Release Note is for the v2.3 COREGen Aurora released in 7.1i IP Update #1 and available in 7.1i IP Update 2, and contains the following:

- New Features

- Bug Fixes

- Known Issues

NOTE: No updates or modifications were made to these cores as a result of 7.1i IP Update 2; thus, the information included below still applies in IP Update 2.

For the installation instructions and design tools requirements for 7.1i IP Update 1, see (Xilinx Answer 21019).

For the installation instructions and design tools requirements for 7.1i IP Update 2, see (Xilinx Answer 21737).


New Features

- Aurora support for Virtex-4 FX devices

- Improved documentation

Bug Fixes

This section will be updated when more information is available

Known Issues

- When attempting to open the User Guide file provided by COREGen, a number of PDF errors occur, including missing images. See the User Guide provided online at:

NOTE: You must be a registered Aurora Member to gain access to this document.

- The INIT_CLK, PMA_INIT and ERROR_COUNT ports have not been locked in the UCF file. Lock the INIT_CLK to an oscillator on the board and the PMA_INIT to a push-button. The ERROR_COUNT port has to be constrained to LEDs.

- A Calibration Block for the MGT must be used with ES Devices. Refer to the Calibration Block User Guide (UG090), or contact your FAE for more details and instructions on how to connect the module to the MGTs DRP and other ports. The MGTs in the Aurora module are instantiated in the "mgt_wrapper.v/.vhd" file. This file can be modified to instantiate and connect the DRP module.

- As characterization of the Virtex-4 MGT progresses, there are recommendations for some attribute settings that are different from the default values in ISE 7.1i. These recommended settings could be different based on the line rate. For 2.5 Gb/s to 3.125 Gb/s, refer to (Xilinx Answer 21672) and (Xilinx Answer 21673). These settings are valid for Aurora at the specified data rates.

- ModelSim 6.1 fails with error: "Fatal: (vsim-3420) Array lengths do not match...." For more details, see (Xilinx Answer 21910).

AR# 21284
日期 02/04/2013
状态 Archive
Type 综合文章