Why is the spread in the data sheet section of the Timing Analyzer not equal to Tdick/Tckdi?
The Tdick and Tckdi represent the internal capture register intrinsic setup and hold times, respectively. These times reflect only the setup and hold time of the internal register, and do not take into account any data path or clock path routing delays prior to that register. However, when specifying the setup and hold time requirements at the pins of the FPGA, as is reported in the data sheet section, the clock and data paths must be taken into account. Because the setup and hold requirements are expressed in relation to separate locations of the input path, the numbers are quite different.