We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21361

LogiCORE SPI-4.2 (POS-PHY L4) v7.2 - Verilog SimPrim: IDELAYCTRL output (RDY) is never asserted


General Description: 

When I run Verilog timing simulation, Sink Core does not go in frame and SnkOof remains High.


This issue is due to NetGen writing out the incorrect representation of the IDELAYCTRL simulation model. This issue is expected to be fixed in 7.1i Service Pack 3.  


To work around this issue, use the simulator switch to turn off the transport delays: 

For MTI: +transport_int_delays

AR# 21361
日期 05/19/2014
状态 Archive
Type 综合文章