In performing Verilog UniSim or SimPrim simulations of the LogiCORE Ethernet Statistics v1.1 and v2.1 Core targeted to Virtex-4 in ModelSim PE, the following memory collision error might occur:
"# Memory Collision Error on RAMB16 : testbench.dut.statistics_gathering.\BU2/U0/ethernet_statistics_64bit/store_lower32_bits .collision_message_task at simulation time 7080.000 ns.
# A read was performed on address 04c0 (hex) of port B while a write was requested to the same address on port A. The write will be successful; however, the read value on port B is unknown until the next CLKB cycle."
Note that this fails only in MTI PE versions of ModelSim (MTI SE simulations work successfully). This is a ModelSim issue and not a core issue. ModelSim is currently investigating the issue.
This Answer Record will be updated as new information becomes available.