UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21411

LogiCORE Binary Counter v8.0 - Why is there a mismatch between the behavioral and timing simulation when using the THRES0?

描述

Keywords: CORE, CORE Generator, CORE Generator, DSP, mismatches

Why is there a mismatch between the behavioral and timing simulation when using the THRES0?

解决方案

This will happen only when SINIT is asserted and the CE is deasserted. To avoid this situation, you should not toggle SINIT when the CE is not asserted.

This is fixed in 7.1i IP Update 2.
AR# 21411
日期 04/09/2009
状态 Archive
Type 综合文章
的页面