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AR# 21412

LogiCORE Binary Counter v8.0 - Why is there a mismatch between the behavioral and timing simulation on the Q output?

描述

Keywords: CORE, CORE Generator, COREGen, DSP, Binary Counter, LogiCORE, Q, behavioral, timing, simulation, mismatches

Urgency: Standard

General Description:
Why is there a mismatch between the behavioral and timing simulation on the Q output?

解决方案

This will happen only when SINIT is asserted and the CE is deasserted. To avoid this situation, you should not toggle SINIT when the CE is not asserted.

This is fixed in 7.1i IP Update 2.
AR# 21412
日期 07/12/2007
状态 Archive
Type 综合文章
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