We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21436

Virtex-4 RocketIO - Why does RocketIO Wizard generate different attribute values for clocking as compared to the Clocking Decision Tree in the RocketIO User Guide?


General Description:  

Some attributes in the RocketIO Wizard such as RXCLKMODE, RXASYNCDIV, TXCLKMODE, and TXASYNCDIV are different from those in the Clocking Decision Flow shown in the User Guide.


There are multiple combinations that build one divide ratio. Although the values are different, the final divider ratio will be same. For example, in the picture, there are two combinations that achieve divide by 20. The red line passes the top dividers /4 and /5, which are the synchronous dividers. Also, the blue line passes the bottom dividers /4 and /5, which are the asynchronous dividers. 


Dividers in receiver
Dividers in receiver


For details about the Receive Clocking Decision Flow or the Transmit Clock Decision Flow, please see the RocketIO User Guide: 


AR# 21436
日期 05/19/2014
状态 Archive
Type 综合文章