AR# 21451

8.1i ISE Simulator (ISIM) - Known Issues with ISE Simulator


Keywords: simulation, problems

This Answer Record contains all the Known Issues for ISE Simulator 8.1i.


Q1. When running a design for 60 seconds or more of simulation time, ISE seems to freeze up and hang. Why does this occur?
A1. This has been improved. Now ISE does not hang, and instead it issues an out of memory error. This problem will be addressed in the ISE 9.1i release of ISE Simulator.

Q2. I cannot view parameters or generics in the hierarchy view. Is there any way to access this information from the simulator?
A2. ISE Simulator does not currently have the ability to display parameter and generics. The simulator reads the information but cannot display it in the GUI. This issue will be fixed in ISE 9.1i.

Q3. After installing an ISE Service Pack, the design does not simulate correctly.
A3. After every Service Pack install, it is a requirement to clean up project files before running through the design. To clean up project files, select Project -> Cleanup Project Files from the Project Navigator toolbar.

Q4. When I type "help" and "HELP," I receive different results in the ISE Simulator console window.
A4. This is a known issue with TCL in the Windows Operating System environment. The TCL interface in the simulation console supports simulation commands as well as all valid System Environment commands, such as HELP. Therefore, "HELP" will access the Windows System help command, and "help" will access the ISE Simulator help. There is no fix scheduled for this issue.

Q5. ISE Simulator is not optimized to be a structural simulator, and this is why some structural netlists (Post-translate/post-MAP/post-PAR) can cause the simulator to hit its maximum limits during compilation.
A5. One way to fix this is to maintain hierarchy in the netlist. Refer to the Synthesis and Simulation Guide for more information, which can be found at:

Q6. When stepping through the code in the console window, the focus changes from the console window to the HDL Editor window as a new file is opened.
A6. This is currently a limitation of the ISE Simulator. To work around this issue, either use the step button (see ISE Simulator help for details), or click back to the main console window as needed. This issue will be addressed in ISE 9.1i.

Q7. When using Generate Expected Results in a design that contains only bidirectional ports, this does not do anything.
A7. The Generate Expected Simulation does not work when using bidirectional signals. This will be fixed in ISE 9.1i.

Q8. ISE Simulator errors out when the ISE design tools are installed in a directory containing spaces.
A8. ISE Simulator will not work if the Xilinx installation is in a directory with spaces. This issue will be fixed in ISE 9.1i.

Q9. Changing the generated HDL language from Verilog to VHDL or vice-versa does not work for schematic designs.
A9. See (Xilinx Answer 20995).

Q10. ISE Simulator runs out of memory on large designs.
A10. This issue will be addressed in ISE 9.1i.

Q11. ISE Simulator dialog boxes are getting truncated when using Linux.
A11. There are multiple reasons why this is happening and it is currently being investigated. This issue will be addressed in ISE 9.1i.

Q12. When running ISE Simulator on Linux, the number in the prompt does not increment when typing "run."
A12. This is a known issue with ISE Simulator 8.1i. This issue will be fixed in ISE 9.1i.

Q13. Can ISE Simulator read third-party binary files?
A13. See (Xilinx Answer 21796).

Q14. The VHDL file written out has an extra period "." in the VHDL library declaration.
A14. See (Xilinx Answer 21880).

Q15. Test Bench Waveform pattern wizard adds random numbers to the end of a pattern.
A15. When a specific non-random pattern is used with the waveform creation tool and then the pattern is changed to a non-random pattern, it seems as if the numbers are now random for some of them. This problem is currently being investigated.

Q16. When running in batch mode, ISIM crashes with a seg fault if there is a "quit" in the customer TCL file.
A16. ISIM engine cannot break at any line and you cannot set any break points. If your custom command file contains quit, or $finish/$stop in a Verilog design with custom command file, ISIM engine is not able to correctly handle these situations. These operations are only allowed in interactive mode. This issue will be fixed in ISE 9.1i.

Q17. ISIM does not support negative setup and hold delays.
A17. This is a limitation of the ISIM engine. This will be supported in ISE 8.2i.

Q18. "ERROR:Simulator:222 - Generated C++ compilation was unsuccessful"
A18. See (Xilinx Answer 23037)

Q19. Cannot simulate bi-directional signals correctly when the signal is driven in the beginning of the testbench waveform - VHDL only
A19. See (Xilinx Answer 23142)
AR# 21451
日期 10/16/2008
状态 Archive
Type 综合文章