There are two configuration issues when using the BitGen "-g EngineeringSample" option noted in the Virtex-4 ES (SX35, LS25, LX60) errata. The issues are listed below:
1. Virtex-4 ES parts will not complete serial configuration from a PROM
The -g EngineeringSample option delays the startup sequence, so there are not enough CCLK cycles when the Master FPGA is driving CCLK. These ES parts will be stuck in the startup sequence and will not become functional. To work around this issue, modify the BitGen startup options so that GWE and GTS are both synchronized to Done. To do this from ISE Project Navigator:
- Right-click Generate Programming File -> Properties.
- From the Startup Option tab, set both Enable Outputs and Release Write Enable to "Done" from the pulldown menu.
2. Virtex-4 ES parts will not complete JTAG configuration with iMPACT
The -g EngineeringSample option and JTAG configuration cause the JTAG configuration to not complete. This BitGen option is used to reduce Vccaux current only in serial configuration mode. For JTAG configuration, Xilinx iMPACT software automatically asserts special JTAG commands to reduce Vccaux current, so this option is not necessary. To work around this issue, remove the BitGen -g option and regenerate the bit file.
For more information, see the Virtex-4 errata: