描述

Back-annotated Verilog and VHDL simulations of the Embedded Tri-mode Ethernet MAC fail to load in timing simulations during SDF annotation. Below are some of the errors generated in ModelSim: 

"# ** Error: (vsim-SDF-3240) emac_vhd_map_vhdl.sdf(11462): Instance '/uut/emacs' does not have a generic named 'thold_clientemac0dcmlocked_clientemac0txclientclkin_negedge_posedge'." 

"# ** Error: (vsim-SDF-3240) emac_vhd_map_vhdl.sdf(11461): Instance '/uut/emacs' does not have a generic named 'thold_clientemac0dcmlocked_clientemac0txclientclkin_posedge_posedge'."

解决方案

This issue will be resolved in ISE 7.1i Service Pack 4.