AR# 21605

Virtex-4 FPGA - Where can I find silicon stepping information specific to Virtex-4 devices?


This answer record contains Frequently Asked Questions (FAQs) regarding silicon stepping specific to Virtex-4 devices. Much of the information contained in this answer record can also be found in the "Production Stepping" section of the Virtex-4 FPGA Data Sheet (DS302):

For general information on silicon stepping, refer to (Xilinx Answer 20947).


Q1. What are the Production stepping levels for Virtex-4 devices?

The current Virtex-4 Production devices are as follows:

  • The LX and SX families have Production Step 1 and Step 2 devices.
  • The FX family has Production Step 0 and Step 1 devices.

LX, SX, and FX families are available as Engineering Sample (ES) devices as well.

Q2. What version of ISE is required for Virtex-4 Production devices?

ISE 7.1i Service Pack 4 or later is required to target any LX- or SX-family Virtex-4 Production devices. This version and service pack level fully support the stepping levels of the LX/SX-family Production devices.

ISE 8.1i Service Pack 2 or later is required to target any FX-family Virtex-4 Production devices. For further information on software support requirements for Virtex-4 ES and Production devices, see Table 1 below.

Q3. How does setting different Virtex-4 stepping levels affect my design?

When setting different stepping levels, note the following:

Insertion of DCM Macro

With CONFIG STEPPING = "ES" or "1" set for LX/SX devices, the insertion of a DCM macro must be performed manually, as described in (Xilinx Answer 21127).

With CONFIG STEPPING="2" set for LX/SX devices or "SCD1," "0," or later for FX devices, the ISE design tools will insert extra logic (~15 slices per DCM) to automatically put the DCMs in auto-calibration mode if the clock input or clock feedback ever stops. See (Xilinx Answer 21435) for more information.

Speed Specifications

Using speed specifications v1.54, all stepping levels report the same timing.

Using speed specifications v1.58 or later, ES, Step 0, Step 1, and Step 2 numbers are available and reflected in your design according to the CONFIG STEPPING setting.

Speed Specifications version 1.54 is available in 7.1i Service Pack 3. Speed Specifications version 1.58 is available in 7.1i Service Pack 4 through a software patch, and in ISE 8.1i by default. To download ISE service packs, go to the Downloads page:

To download the patch for 7.1i Service Pack 4 software, see (Xilinx Answer 22197).

For more information about speed specification versions, refer to (Xilinx Answer 12201).

Q4. What stepping values are reported when I run Speedprint?

Speedprint uses the default value for the device. For example, Speedprint reports stepping level 1 values for LX/SX Virtex-4 devices (see Q8 below). If any ES devices have different timing than the default stepping values, the differences will be listed in the corresponding errata.

Q5. Can I download a Step 1 bitstream to a Step 2 device?

Yes, as new Production stepping is introduced, it will be backward-compatible. Consequently, you can download a bitstream from a lower step to a higher step device (in this case, using a Step 1 bitstream for a Step 2 device).

Tables 1 and 2 describe bitstream compatibility for LX, SX, and FX devices between ES and Production step devices. The compatibility is determined based on designs that have been created according to the software requirements described in Tables 3 and 4 below.

Table 1 - Virtex-4 LX/SX Bitstream Compatibility
Table 1 - Virtex-4 LX/SX Bitstream Compatibility

NOTE 1: This note only effects the LX25, LX60 and SX 35. Bit streams are compatible, except for a small timing difference in system-synchronous designs (the difference is documented in the ES errata). Most designs are not affected by this difference. For assistance in verifying timing for a different step part, contact your local Xilinx FA E.

NOTE 2: Manual insertion of the DCM macro, described in (Xilinx Answer 21127), is not required. ISE design tools will automatically insert a macro if the macro is not inserted manually. See (Xilinx Answer 21435) for more information.

NOTE 3: If you are using Step 1 silicon with a Step 2 bitstream, the Step 2 bitstream must have the Autocalibration turned off and the DCM Macro manually inserted.

Table 2 - Virtex-4 FX Bitstream Compatibility
Table 2 - Virtex-4 FX Bitstream Compatibility

NOTE 1: When migrating up to CES4 or CES5 from CES3, a new bitstream must be generated with the correct CONFIG STEPPING setting. See Table 4 below for the correct setting.

NOTE 2: See Errata for the differences between FX Step 0 and Step 1 silicon.

Q6. What are valid CONFIG STEPPING settings in ISE design tools for Virtex-4 devices? What happens if I enter an invalid CONFIG STEPPING value?

Valid CONFIG STEPPING settings for LX/SX devices are "ES," "0," "1," and "2."

Valid CONFIG STEPPING settings for FX devices are "ES," "SCD1, "0" and "1."

If an invalid value is entered, the ISE design tools (MAP) issue an error.

Q7. What is the default stepping level for Virtex-4 devices in ISE 7.1i Service Pack 4? Will the default change?

The default CONFIG STEPPING setting for LX/SX is "1."

The default CONFIG STEPPING setting for FX is "0."

NOTE: If you are targeting an ES device, you must set the CONFIG STEPPING as listed in the corresponding errata. The LX/SX/FX ES device is not equal to the LX/SX/FX Production device. Consequently, an FX ES bitstream where CONFIG STEPPING = ES should not be downloaded to FX stepping level 0 devices.

It is possible that the default value of stepping will change in future ISE versions. To prevent this from affecting your design, Xilinx strongly recommends that you always specify CONFIG STEPPING for Virtex-4 designs.

Q8. I generated a bitstream to target ES devices in an older version of software. Do I have to regenerate my bitstream in ISE 7.1i Service Pack 4?

Yes, for LX/SX family devices, the minimum software requirement is ISE 7.1i Service Pack 4. Please ensure that the appropriate CONFIG STEPPING value is set. See Table 2 for the appropriate software required to generate the bitstream for FX ES and production devices.

Q9. Is there a cross-reference table for the information above?

The following two tables summarize the information above:

Table 3 - Virtex-4 LX/SX Software Requirements
Table 3 - Virtex-4 LX/SX Software Requirements

* NOTE: See (Xilinx Answer 22197).

Table 4 - Virtex-4 FX Software Requirements
Table 4 - Virtex-4 FX Software Requirements

*NOTE: See (Xilinx Answer 22197).
**NOTE: SW Requirement and Minimum Speed Specification are speed grade dependant.
-10 v1.58 8.1i Service Pack 2 (SP2)
-11 v1.62 8.2i Service Pack 3 (SP3)
-12 v1.65 9.2i Service Pack 1 (SP1)

Q10. How do I determine the stepping level of my device if I cannot read the top marking?

(Xilinx Answer 1067) describes how to determine the stepping level from the device top mark. When the top marking is not readable or covered by heatsink, the stepping can be determined by reading the JTAGID from ISE iMPACT as noted below. Compare the device version obtained with Table 3 or Table 4 to determine the device stepping level.

You can obtain the JTAG Rev ID of a device from iMPACT with the "Get Device ID" operation. The following is an example of the log file:

// *** BATCH CMD : ReadIdcode -p 1
Validating chain...
Boundary-scan chain validated successfully.
'1': IDCODE is '00000001011010110100000010010011'
'1': IDCODE is '016b4093' (in hex).
'1': : Manufacturer's ID =Xilinx xc4vlx60, Version : 0

Table 5 - Virtex-4 LX/SX Stepping vs. JTAG IDCODE
Table 5 - Virtex-4 LX/SX Stepping vs. JTAG IDCODE

The JTAG Rev ID of a device can be found in the Virtex-4 data sheet (DS302) Table 62:JTAG ID Code by Step, or in the errata for that device.

NOTE: A higher functionality device can be shipped in place of a lower functionality device, so some parts marked Step 1 might have a JTAG ID code that matches up with Step 2. You should always design for the lower-functionality device.

AR# 21605
日期 01/22/2013
状态 Active
Type 综合文章