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AR# 21653

8.1 CPLDFit - The fitter report equations in VHDL are missing CE port connection


General Description: 

The fitter report equations in VHDL for the FDCPE and FTCPE are missing a port connection. The legend shows that these components have six ports; however, the equations show five. How do I identify which signals connect to which ports?


The port connection that is missing is the Clock Enable (CE) connection. If a CE is used, six ports are shown. If a CE is not used, only five are shown and you can assume that the CE is '1'. 


This issue will be fixed in a future release of the design tools.

AR# 21653
日期 05/08/2014
状态 Archive
Type 综合文章