We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 2167

FPGA/Design Compiler: How to specify slew rates in Synopsys FPGA Compiler or Design Compiler?


Keywords: FPGA Compiler, Slew Rate, Slew Control, Synopsys, Compiler

Synopsys and Xilinx define slew rates in opposite terms. Synopsys uses slew control, whereas Xilinx uses slew rate.

For example a Synopsys HIGH slew control is equivalent to a Xilinx SLOW slew rate. And by the same definition, the Synopsys NONE or LOW slew control is equivalent to the Xilinx FAST slew rate.


Use the following commands to your Compiler script:

set_pad_type -slewrate HIGH all_outputs ()
/* this sets the slew rate for all the outputs to SLOW */

set_pad_type -slewrate NONE {portnames}
/* this sets the slew rate for certain outputs to FAST */

For more information please refer to the Synopsys for FPGAs Interface/Tutorial Guide pages 5-9 to 5-15.

NOTE: These script directives will not work for Virtex designs. The workaround is to instantitate the appropriate buffers (i.e. OBUF_F) where needed and then modify your script to exclude those ports in the set_port_is_pad stage.
AR# 2167
日期 04/25/2007
状态 Archive
Type 综合文章