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AR# 21724

11.1 Virtex-4 PAR - "ERROR:Place:645 - A clock IOB clock component is not placed at an optimal clock"


When I run a design that has Clock inputs through Clock Capable I/Os, PAR issues the following error message:
"ERROR:Place:645 - A clock IOB clock component is not placed at an optimal clockIOB site The clock IOB component <CLK> is placed at site IOB_X1Y84. Theclock IO site can use the fast path between the IO and the Clock buffer/GCLKif the IOB is placed in the master Clock IOB Site. If this sub optimalcondition is acceptable for this design you may set the environment variableXIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING to demote this message to a WARNING andallow your design to continue."


This error indicates that the design is not using a Clock-IOB site to drive a global clock buffer. Clock-IOB sites have a dedicated routing path to global buffers with reduced routing delay.
NOTE: The most common design mistake leading to this error results from a single-ended clock input being LOC'd to the N side of a differential pair of clock-capable I/O. Only the P side of the differential pair has the dedicated routing resource. When choosing a Global Clock IOB site, it is not enough to choose a site with "GC" in the pin definition. It is also necessary to choose the "P" side of a differential pair. For example, a pin definition of IO_L1P_GC_CC_LC_3 is valid as a Global Clock IOB site, whereas IO_L1N_GC_CC_LC_3 is not.
If the increased delay associated with the use of general routing resources is acceptable, the XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING environment variable can be set to reduce this error to a warning:
Linux and Solaris
If this extra routing delay is not acceptable, the input should be constrained to a valid Clock-IOB site.
To check what type of I/O the Clock has been constrained to, refer to the Virtex-4 Packaging and Pinout Specification:
Navigate to FPGA Device Families -> Virtex-4 -> Virtex-4 Packaging and Pinout Specification.
For more general information about setting ISE environment variables, see (Xilinx Answer 11630).
If the input in question is unconstrained, the error might be occurring because the design is infeasible from the Global Clock Component placement point of view. The placement of connected global clock components like Clock-IO, BUFGCTRL, DCM, PMCD, PLL and GT11CLK are governed by strict rules, all of which have to be simultaneously satisfied. Please refer to the Global Clocking Section of the User Guide for a complete list of all global clock placement rules.
It is also possible that PAR was unable to find a feasible placement solution when such a solution exists. You can help direct PAR to a good solution by LOCing the comps indicated in the error message to legal sites.
AR# 21724
日期 12/15/2012
状态 Active
Type 综合文章
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 QPro/R
  • Virtex-4 SX
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • Less