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AR# 21733

8.1 PACE - When I enter a design in ECS, the port name in PACE will be the component name rather than the signal name


When I enter a design in schematic drawing and use PACE to constrain the pins, the port that I see in PACE is not the signal name. Instead, it is another schematic port list. How do I work around this?


The reason is that PACE looks at the first module it sees in the HDL file, which is not necessarily the top level. To work around this issue, use NGD for the source instead of HDL (post translate), or place the top-level module at the beginning of the HDL file.

AR# 21733
日期 12/15/2012
状态 Active
Type 综合文章