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AR# 21797

FPGA Configuration - Are there any minimum requirements for CCLK frequency?

描述

General Description:

Are there any minimum requirements for CCLK frequency?

解决方案

As long as CCLK frequency and high/low times are met, there are no duty cycle requirements. The CCLK can be run as slow as desired. All of the timing specifications for CCLK are listed in the appropriate device data sheet. The data sheets contain all of the required timing specifications.

AR# 21797
日期 12/15/2012
状态 Active
Type 综合文章
的页面