AR# 2185: SYNPLIFY: How to change the output slew rate using the xc_fast attribute?
AR# 2185
SYNPLIFY: How to change the output slew rate using the xc_fast attribute?
Description
Keywords: Synplify, SDC, Verilog, VHDL, xc_fast, xc_slow, FAST
Urgency: Standard
General Description: How to change the output slew rate using the xc_fast attribute?
The slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-critical signals. For critical signals, attach the FAST property to output primitives, output pads, bidirectional pads in the UCF file. Or, through Synplify, apply the xc_fast in the HDL or the SDC file.
Use this attribute to decrease the transition time for the output driver and increase the noise in the system. Synplify provides certain attributes that get passed into the implementation netlist for Xilinx place and route that affect the input setup times and output transition times for your I/Os.
// D flip-flop always @(posedge CLK) Q_OUT <= D_IN;
endmodule
3
-- VHDL
library IEEE; use IEEE.std_logic_1164.all; library synplify; use synplify.attributes.all;
entity fast_ex is port (CLK : in STD_LOGIC; D_IN : in STD_LOGIC_VECTOR (3 downto 0); Q_OUT : out STD_LOGIC_VECTOR (3 downto 0)); attribute xc_fast of Q_OUT : signal is true; end fast_ex;
architecture XILINX of fast_ex is
begin
-- D flip-flop process(CLK) begin if rising_edge(CLK) then Q_OUT <= D_IN; end if; end process;