AR# 2185: SYNPLIFY: How to change the output slew rate using the xc_fast attribute?
SYNPLIFY: How to change the output slew rate using the xc_fast attribute?
Keywords: Synplify, SDC, Verilog, VHDL, xc_fast, xc_slow, FAST
General Description: How to change the output slew rate using the xc_fast attribute?
The slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-critical signals. For critical signals, attach the FAST property to output primitives, output pads, bidirectional pads in the UCF file. Or, through Synplify, apply the xc_fast in the HDL or the SDC file.
Use this attribute to decrease the transition time for the output driver and increase the noise in the system. Synplify provides certain attributes that get passed into the implementation netlist for Xilinx place and route that affect the input setup times and output transition times for your I/Os.