描述

My design ignores the output of the block RAM at certain times. Do the setup and hold times of the ADDRESS inputs still need to be met, even if Write Enable (WE) is deasserted?

解决方案

When a port is enabled, the setup and hold specifications of the ADDRESS inputs should never be violated, even if WE is deasserted.

For Virtex-II, Virtex-II Pro, Virtex-4, Virtex-5, Virtex-6, 7 Series and UltraScale/UltraScale+ FPGAs, when a block RAM port is enabled, all address transitions must meet the setup and hold time of the ADDR inputs with respect to the port clock. 

The setup and hold requirements for the block RAM inputs are listed in the device data sheet. 

The requirements must be met even when the read data output is ignored by the user and WE is deasserted. Otherwise, the block RAM contents might be unreliable.

There are some instances in which you might not be able to meet these requirements, for example, if there is a multi-cycle path on the address input signals. 

To work around this, disable the port via ENA/ENB during the time that the address inputs do not meet setup and hold requirements.

De-asserting ENA/ENB will disable the port so that violating the address input setup and hold requirements will not affect block RAM contents. 

Assert ENA/ENB again when resuming normal read and write functionality.

The Virtex-II, Virtex-II Pro, Virtex-4, Virtex-5, Virtex-6, 7 Series and UltraScale/UltraScale+ FPGA data sheets are located here:

https://www.xilinx.com/support/documentation/index.htm

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