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AR# 21871

State Diagram Editor - Why are some of the outputs high during reset?


Using the ISE State Diagram Editor to generate VHDL code, the State machine looks ok, but the generated VHDL code appears to have incorrect initialization of some signals. Should not every output be set to zero when reset is active?


Two cases will cause an output to be set to "1" when the asynchronous reset is applied: 


- If the signal is set to "1" in the first (reset) state of the state machine 


- If the signal is active LOW. In this case, when reset is applied, the active low signals will automatically be set to inactive state (HIGH)

AR# 21871
日期 05/19/2014
状态 Archive
Type 综合文章