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AR# 21894

MIG 007 Rel 5 - DDR1 design synthesized with XST fails when device is heated


Keywords: MIG, DDR, DQS, delay, Virtex-II Pro, Temperature

When I use MIG 007 Rel 5 to generate a DDR1 design and target the side banks of my Virtex-II Pro device, i.e., banks 2,3 or 6,7, the design runs okay but fails when the device is heated. The design runs okay when the device is cooled down again.


There is an issue whereby the following inversions are being implemented in a LUT:

-- dqsx_delayed_col0 negated signals
dqs0_delayed_col0_n <= not dqs0_delayed_col0;
dqs1_delayed_col0_n <= not dqs1_delayed_col0;
-- dqsx_delayed_col1 negated signals
dqs0_delayed_col1_n <= not dqs0_delayed_col1;
dqs1_delayed_col1_n <= not dqs1_delayed_col1;

To verify that you are experiencing this issue, in your PAR report check the delay on the dqs_delayed net. The delay should be of the order of 400ps. If the problem exists, it would occur at approximately 1.0 ns.

To overcome this issue, do the following;

1. In data_read_controller.vhd, comment out the syn_keep attributes:
-- Directive for synthesis
--attribute syn_keep of dqs0_delayed_col0_n : signal is true;
--attribute syn_keep of dqs1_delayed_col0_n : signal is true;
-- Directive for synthesis
--attribute syn_keep of dqs0_delayed_col1_n : signal is true;
--attribute syn_keep of dqs1_delayed_col1_n : signal is true;

2. Allow logic optimization across hierarchical boundaries. Then set the hierarchy switch in MAP, as suggested in (Xilinx Answer 20902).

AR# 21894
日期 04/06/2009
状态 Archive
Type 综合文章