UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21911

Virtex-4 XtremeDSP Slice and MAP 7.1.03i - Why are the clock enables on my XtremeDSP Slice (DSP48) being disabled? Why is there no output from my XtremeDSP Slice (DSP48), or why is the POUT zero?

描述

Keywords: GND, VCC, AREG, BREG, MREG, PREG, A_REG, B_REG, M_REG, P_REG

Why are the clock enables on my XtremeDSP Slice (DSP48) being disabled? Why is there no output from my XtremeDSP Slice (DSP48), or why is the POUT zero?

解决方案

This problem has been fixed in the latest 7.1i Service Pack available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 7.1i Service Pack 4.

To work around this issue in ISE 7.1i Service Pack 3, set the following environment variable:
XIL_MAP_NO_DSP_AUTOREG = 1

NOTE: A side effect of this work-around is that registers will not be merged into the XtremeDSP Slice (DSP48), and this might adversely impact performance.
AR# 21911
日期 09/04/2008
状态 Archive
Type 综合文章
的页面