UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21922

7.1 System Generator for DSP - Why do I have a cl_clr pin at the top level of my design? My design does not work in hardware after generating a bitstream from the Project Navigator Project when using the HDL Netlist flow. Why?

描述

General Description:

Why do I have a cl_clr pin at the top level of my design? My design does not work in hardware after generating a bitstream from the Project Navigator Project when using the HDL Netlist flow or Bitstream flow. Why?

解决方案

When System Generator for DSP 7.1 creates a design, it adds a ce_clr pin that is not necessary for most designs.

To work around this issue, use the HDL Netlist flow. Change the following line in the <design name>_clk_wrapper.vhd:

ce_clr_sysgen <= ce_clr;

to

ce_clr_sysgen <= '0';

This issue is addressed in System Generator for DSP 8.1.

AR# 21922
日期 12/15/2012
状态 Active
Type 综合文章
的页面