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AR# 21990

LogiCORE PCI Express - v2.1.1 PCI Express Core and v 1.1 PIPE UG states that command register bits 1 and 0 are reserved. Is this correct?

描述

General Description: 

In Table 5-10 of the PIPE UG and Table 4-8 of the v2.1.1 UG, bits 1 and 0 of the "cfg_command" register output from the core are marked reserved. Is this correct?

解决方案

These bits have the same meaning in PCI Express as they do in PCI. Please see section 6.2.2 of the v3.0 PCI Specification for a detailed explanation of these bits. 

 

Bit 1 enables the device's ability to respond to memory request, and bit 0 enables the device's ability to respond to I/O request. If these bits are not set, the core will not respond to memory or I/O write and read commands. 

 

These bits are set by the host by issuing configuration writes to the command register located in the PCI configuration space at address 0x04.

AR# 21990
日期 05/19/2014
状态 Archive
Type 综合文章
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