When regional clocking is selected for the Sink or Source cores, the tools might have issues placing the regional clocks. The tool might fail to route the TSClk because of poor placement of the BUFRs.
You might receive following error message from PAR:
"Phase 8: 61 unrouted; (0) REAL time: 13 mins 13 secs
IMPORTANT MSG: UNROUTABLE DESIGN; CHANGE PLACEMENT or EASE CONSTRAINTS
Phase 9: 61 unrouted; REAL time: 13 mins 16 secs
Phase 10: 61 unrouted; (0) REAL time: 13 mins 38 secs
Total REAL time to Router completion: 13 mins 44 secs
Total CPU time to Router completion: 13 mins 13 secs"
Adding the following constraints the UCF File can resolve the issue:
Sink: INST "RS*" LOC = "Bank5"; INST pl4_lite_snk_clk0/* AREA_GROUP = AG_pl4_lite_snk ;
Source: INST pl4_lite_src_clk0/* AREA_GROUP = AG_pl4_lite_src ;