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AR# 22013

LogiCORE SPI-4.2 (POS-PHY L4) Lite v3.0 - Synplicity synthesis attributes incorrect in User Clk Module causes offset timing error in PAR

描述

General Description: 

When Synplicity is selected in the COREGen project options, the resulting Sink user clocking module DCM synthesis attributes are incorrect. There are five total attributes, but only three are recognized by the tools. This causes the DCM to be configured incorrectly and causes timing failures on the OFFSET constraints when the design is run through PAR.

解决方案

To fix this problem, you will need to replace the following constraints in the user clock module. 

 

Replace:  

 

/* synthesis xc_props="CLK_FEEDBACK = 1X, DLL_FREQUENCY_MODE = LOW, CLKOUT_PHASE_SHIFT = FIXED" */; 

/* synthesis xc_props="PHASE_SHIFT = 62, DESKEW_ADJUST = SOURCE_SYNCHRONOUS" *///; 

 

With: 

 

/* synthesis xc_props="CLK_FEEDBACK = 1X, DLL_FREQUENCY_MODE = LOW, CLKOUT_PHASE_SHIFT = FIXED , PHASE_SHIFT = 62, DESKEW_ADJUST = SOURCE_SYNCHRONOUS" */;

AR# 22013
日期 05/19/2014
状态 Archive
Type 综合文章
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