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AR# 22042

LogiCORE SPI-3 PHY v4.0 - DCM placement constraints needed in UCF (alos applies to SPI-3 Link core)

描述

Urgency: Standard  

 

General Description: 

When running PAR with the SPI-3 PHY Core, the clock pin and DCM will be placed on opposite sides of the chip, causing timing failures due to large clock delays.

解决方案

To resolve this issue, you will need to lock down the DCM near the SPI-3 Core. Add the placement constraint for the DCM and the clock pin.

AR# 22042
日期 05/19/2014
状态 Archive
Type 综合文章
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