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AR# 22049

8.1i/7.1i XST - Can I implement an incomplete design in ISE?


Keywords: I/O, pre-assign, pre-assignment, preassign, LOC, IOSTANDARD, XST, NGDBuild, Translate, MAP, PAR, PAD, incomplete, design, feature

A new feature has been added to the 7.1i ISE toolset: Pin Preassignment. What is this feature all about?

Designs that are not yet fully coded might still have layout requirements. Pin assignments, voltage standards, banking rules, and other board requirements might be in place long before the design has reached the point where these constraints can be applied. The Pin Preassignment feature allows the pin-out rules of the design to be determined before the design logic has been completed.


This information will be available in the 8.2i Constraints Guide

To use the Pin Preassignment feature, provide the complete list of ports in your top-level design, and then assign I/O constraints to them. Even if the ports are not used by any logic in the design (i.e., no loads for input pins, no sources for output pins), they can still receive constraints and be kept through implementation. Assign LOC or IOSTANDARD constraints in the UCF just like for any I/O pin, and these requirements will be annotated in the database. PACE can be used to assign pin locations, banking groups or voltage standards, and DRC checks can be run. The final ".PAD" report will contain any pins that have logic or constraints associated with them.

This implementation of the design is incomplete and cannot be downloaded to the hardware. You should expect these errors during the DRC phase of bitstream generation (BitGen):

"ERROR:PhysDesignRules:368 - The signal <D_OBUF> is incomplete. The signal is not driven by any source pin in the design."
"ERROR:PhysDesignRules:10 - The network <D_OBUF> is completely unrouted."

To trim any unused ports from the design, remove the associated constraints. The Translate (NGDBuild) phase will trim these unused pins.

In this example, there are six top-level ports. Only three (clk, A, C) are currently used in the design. Of the remaining three ports, B will be kept because it has a LOC constraint, D will be kept because it has an IOSTANDARD constraint, and E will be trimmed because it is completely unused and unconstrained.

module design_top(clk, A, B, C, D, E);
input clk, A, B;
output reg C, D, E;

always@(posedge clk)
C <= A;



NET "A" LOC = "E2" ;
NET "B" LOC = "E3" ;
NET "C" LOC = "B15" ;

This issue has been fixed and addressed with the release of ISE 9.1i.
AR# 22049
日期 01/08/2009
状态 Archive
Type 综合文章