UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22103

NetGen - If hierarchy is kept, a Global_logic0/Global_logic1 is generated without a driver in the timing simulation netlist

描述

The Global_logic0/Global_logic1 should be connected to the X_ZERO/X_ONE components. However, when the hierarchy is maintained, NetGen sometimes does not make this connection and signals that should be Global_logic0 are all "U" in timing simulation.

解决方案

To work around this issue, flatten the design.

This issue is fixed in ISE 8.1i Service Pack 2, released in February 2006.

The following environment variable must be set when using ISE 8.1i Service Pack 2 and above:

XIL_NETGEN_DRIVE_PWR_GND = 1

AR# 22103
日期 12/15/2012
状态 Active
Type 综合文章
的页面