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AR# 22111

MIG 1.3 - Is it possible to generate a DDR2 controller?


Keywords: memory, interface, generator, ddr

I am using MIG 1.3 and would like to generate a DDR2 controller, but when I open the tool, I find that the DDR2 option is disabled. What am I doing incorrectly?

Is it possible to generate a DDR2 controller using MIG 1.3?


Yes, it is possible to generate a DDR2 controller using MIG 1.3. However, the DDR2 controller is available only in Verilog. Therefore, if you have VHDL selected as your simulation language in your project
options, it will not be possible to select a DDR2 design.

Change the simulation language to Verilog, and you should be able to select the DDR2 controller and generate a design.

For a full list of the MIG 1.3 release notes, please see (Xilinx Answer 21971). It is intended to introduce VHDL support for the DDR2 controller in a later release of MIG (MIG 1.4).
AR# 22111
日期 04/06/2009
状态 Archive
Type 综合文章