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AR# 22134

MIG 1.3 - DDR controller failure after reset for frequencies between 200-220 MHz

描述

Keywords: memory, interface, generator, ddr, reset, bug, controller, mig

After reset, the tap controller logic does not always function correctly at all operating frequencies. We noticed a failure rate of around 2% with the controller in the 200 to 220-MHz operating range. When is this going to be fixed?

解决方案

The new tap controller logic resolves this issue in MIG 1.4.

There is an update (new 'comp16_tap_ctrl.v' file) available via Technical Support:
http://www.xilinx.com/support/mysupport.htm

AR# 22134
日期 04/06/2009
状态 Archive
Type 综合文章
的页面