UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22166

7.1i NetGen - The X_ODDR module performs setup and hold checks relative to the incorrect clock edge when DDR_CLK_EDGE attribute is set to "OPPOSITE_EDGE"

描述

Keywords: simulate, SimPrim, output, timing

Urgency: Standard

General Description:
During timing simulation of the X_ODDR module, when DDR_CLK_EDGE attribute is set to "OPPOSITE_EDGE", setup and hold checks of port D2 are relative to incorrect clock edge. All of the setup and hold checks should be with respect to the negative edge of the clock, not the positive edge.

解决方案

Currently, there is no way to work around this issue.

This issue is fixed in 8.1.
AR# 22166
日期 11/17/2008
状态 Archive
Type 综合文章
的页面